Setting up Hold / Clear (Address "10")

Buffer Memory Address "10"

This is used to keep analog output values as previous values or output an offset value when a PLC stops or an error occurs in it.
0 : Clear , 1 : Hold
To make hold/clear setup available, requesting to set up operation condition(Y0A) is to be set and reset.
Default value is clear.
As a set value is stored in EEPROM, the A/D module is operated as previously set value even though the power is on and off.

The combination of analog output statuses is as follows.

CM1-DA04I, CM1-DA08I

Enabling / Disabling to D/A convert (Buffer Memory Address "0")	Enable			Disable
Enabling / Disabling output by channels (Buffer Memory Address "23")	Enable		Disable	-
Setting up Hold & Clear (Buffer Memory Address "10")	Hold	Clear	-	-
PLC CPU RUN, PAUSE	A digital value is D/A converted and the result is output in analog value.		4mA	4mA
PLC CPU STOP	Keep	4mA	4mA	4mA
PLC CPU Heavy-Error	Keep	4mA	4mA	4mA

CM1-DA04V, CM1-DA08V

Enabling / Disabling to D/A convert (Buffer Memory Address "0")	Enable						Disable
Enabling / Disabling output by channels (Buffer Memory Address "23")	Enable				Disable		-
Setting up Hold & Clear (Buffer Memory Address "10")	Hold		Clear		-		-
Digital Input Type (Buffer Memory Address "22")	-192 ~16191	-8192 ~8191	-192 ~16191	-8192 ~8191	-192~ 16191	-8192 ~8191
PLC CPU RUN, PAUSE	A digital value is D/A converted and the result is output in analog value.				-10V	0V	-10V
PLC CPU STOP	Keep		-10V	0V	-10V	0V	-10V
PLC CPU Heavy-Error	Keep		-10V	0V	-10V	0V	-10V

CM1-DA04VA, CM1-DA08VA

Enabling / Disabling to D/A convert (Buffer Memory Address "0")	Enable			Disable
Enabling / Disabling output by channels (Buffer Memory Address "23")	Enable		Disable	-
Setting up Hold & Clear (Buffer Memory Address "10")	Hold	Clear	-	-
PLC CPU RUN, PAUSE	A digital value is D/A converted and the result is output in analog value.		0V	0V
PLC CPU STOP	Keep	0V	0V	0V
PLC CPU Heavy-Error	Keep	0V	0V	0V