Shared Memory - High-speed Counter

Address

Set Value

Initial Value

R/W

CH1

CH2

Hexa

Deci

Hexa

Deci

0H

0

20H

32

Currently Counted Value(Signed 32-bit)

L

0

R

1H

1

21H

33

H

2H

2

22H

34

Flag Indicating Overflow Detected

(If overflow in Linear Counting, 1)

0

R

3H

3

23H

35

Flag Indicating Sampling-counted or Periodic-pulse-counted

0

R

4H

4

24H

36

Latch-counted Value

L

0

R

5H

5

25H

37

H

6H

6

26H

38

Sampling-counted Value

L

0

R

7H

7

27H

39

H

8H

8

28H

40

Previous Periodic-pulse-counted Value

L

0

R

9H

9

29H

41

H

AH

10

2AH

42

Current Periodic-pulse-counted Value

L

0

R

BH

11

2BH

43

H

CH

12

2CH

44

Not Use

-

-

DH

13

2DH

45

EH

14

2EH

46

FH

15

2FH

47

10H

16

30H

48

Preset Value(Signed 32-bit)

L

0

R/W

11H

17

31H

49

H

12H

18

32H

50

Set Coincidence Comparison Value 1(Signed 32-bit)

L

0

R/W

13H

19

33H

51

H

14H

20

34H

52

Set Coincidence Comparison Value 2(Signed 32-bit)

L

0

R/W

15H

21

35H

53

H

16 H

22

36H

54

Set Lowest Limit Value of Ring Counting(Signed 32-bit)

L

0

R/W

17 H

23

37H

55

H

18 H

24

38H

56

Set Upper Limit Value of Ring Counting(Signed 32-bit)

L

0

R/W

19 H

25

39H

57

H

1A H

26

3AH

58

Counting Function Setup

(0:Disable 1:Latch 2:Sampling 3:Periodic Pulse)

0

R/W

1B H

27

3BH

59

Sampling / Periodic Time

0

R/W

1C H

28

3CH

60

Counting Mode(0:Linear  1:Ring)

0

R/W

1D H

29

3DH

61

Pulse Input Method

( 0:1-phase 1-multiple(H/W Input to Phase B)

1:1-phase 1-multiple(S/W Input to Phase B)

2:2-phase 2-multiple(H/W Input to Phase B)

3:2-phase 2-multiple(S/W Input to Phase B)

4:CW/CCW 5:2-phase 1-multiple 6:2-phase 2-multiple

7:2-phase 4-multiple)

7

R/W

1E H

30

3EH

62

Counting down by software

0

R/W

1F H

31

3FH

63

Not Use

-

-