Output Signals - High-speed Counter

Channel

HSC <- CPU

Operation Timing

Description

CH1

CH2

Y00

Y08

Requesting to Reset Coincidence Signal 1

These are turned on to reset "Counted Value Coincident 1" (X02(X09)).

Y01

Y09

Requesting to Preset

These are turned on to preset.

Y02

Y0A

Enabling Coincidence Output

These are turned on to enable to output "Counted Value Coincident"(X02/X09 X06/X0D) to an outer terminal.

Y03

Y0B

DRRAM REQUEST

These are turned on to make the contents of DPRAM available.

Y04

Y0C

Enabling to Count

These are turned on to enable to count.

Y05

Y0D

Requesting to Reset Detecting Outer Presetting

These are turned on to reset "Detecting Request for Outer Presetting (X04(X0B))".

Y06

Y0E

Requesting to Start to Count

These are turned on to start the latch or the sampling counting function.

These are turned on to start the disabling to count or the periodic pulse counting.

Y07

Y0F

Requesting to Reset Coincidence Signal 2

These are turned on to reset "Counted Value Coincident 2"(X06(X0D)).