Input and Output Signal - PLCS AD/DA
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Mar 26, 2024
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Sign direction(CPU ← A/D,D/A) | Sign direction(CPU → A/D,D/A) | ||
Input | Signal | Output | Signal |
X00 | A/D module Ready | Y10 | Reserved |
X01 | Reserved | Y11 | |
X02 | Finishing operating condition setting | Y12 | Requesting operating condition setting |
X03 | CH.1 High Alarm value | Y13 | DA CH1 output Enable |
X04 | CH.2 High Alarm value | Y14 | DA CH2 output Enable |
X05 | CH.1 Low Alarm value | Y15 | Reserved |
X06 | CH.2 Low Alarm value | Y16 | |
X07 | Reserved | Y17 | |
X08 | Y18 | ||
X09 | Y19 | ||
X0A | Y1A | ||
X0B | Y1B | ||
X0C | Y1C | ||
X0D | Y1D | ||
X0E | Y1E | ||
X0F | Module Error flag | Y1F | Flag to request error clear |
Refer to A/D module in Chapter 7 and D/A module in Chapter 8 for more detailed description for input / output signals.