Internal I/O and Shared Memory

Internal I/O Table

Input Signals		Output Signals
Point	Description	Point	Description
X00	Module Ready	Y00
X01	Zero/Tare Req. Processed	Y01
X02	Ch1 Command Ack.	Y02	Ch1 Command
X03	Ch2 Command Ack.	Y03	Ch2 Command
X04	Ch3 Command Ack.	Y04	Ch3 Command
X05	Ch4 Command Ack.	Y05	Ch4 Command
X06	Ch1 Batch Running	Y06	Ch1 Zero Command (Req.)
X07	Ch2 Batch Running	Y07	Ch2 Zero Command (Req.)
X08	Ch3 Batch Running	Y08	Ch3 Zero Command (Req.)
X09	Ch4 Batch Running	Y09	Ch4 Zero Command (Req.)
X0A	Ch1 Error	Y0A	Ch1 Tare Command (Req.)
X0B	Ch2 Error	Y0B	Ch2 Tare Command (Req.)
X0C	Ch3 Error	Y0C	Ch3 Tare Command (Req.)
X0D	Ch4 Error	Y0D	Ch4 Tare Command (Req.)
X0E		Y0E
X0F		Y0F

WG0nA module has its own internal I/O signals. These signals are not actually connected to real inputs and outputs. But those signals provide a simple method for command issuing and status monitoring between CPU and WG0nA.

Input Signals

Input signals provide the most frequently referencing status flags of WG0nA module, not only the module ready signal (X0), but also the command acknowledge (X2/3/4/5), batch control status (X6/7/8/9) and error status (XA/B/C/D) of each channel. X1 signal is a response(OK) signal of zero/tare command(request, Y6..YD). X1 is turned on when the zero/tare command was processed successfully, and turned off when all zero/tare command(request) signals are turned off.

Output Signals

Outputs are used as a command issuing signals from CPU. Three kinds of commands can be issued by these outputs.

General Purpose Command (Y2/3/4/5) :

Most of commands are issued by this signal. Before issuing this signal, the command code should be assigned to the command main code (offset 7, 22, 37 or 52) and command sub code (offset 8-9, 23-24, 38-39 or 53-54) fields of shared memory. Following table shows the possible command main codes.

Command	Name	Function
H0001 (1)	Error Clear	Clear the current error code and state. If the trouble which caused the error was removed, the error code will be cleared to zero and error signal (XA/B/C/D) will be turned off.
H0002 (2)	Batch Start	Starts the batch process. Before issuing this command the weighing mode and the related configurations should be set in shared memory.
H0003 (3)	Batch Stop	Stops the current executing batch process. After this command, all the output signals will be turned off.
H0004 (4)	Calibration	The measured raw value at the time when this command was issued will be treated as the zero.
H0005 (5)	Set Span	To perform a span calibration place the calibration mass onto the scale, and then issue this command with the size of the calibration mass in command sub-code. Span calibration must be performed after zero calibration.
H0006 (6)	Store the Calibration Data	All the calibration data will be stored in non-volatile memory of WG0nA module. These calibration data will be restored automatically at every power on.
H0007 (7)	Zero Reset	Reset the current zero. This command makes the gross weight be same with the measured weight.
H0008 (8)	Tare Reset	Reset the current tare. This command makes the net weight be same with the gross weight.

Following timing chart shows the step of issuing the command to the WG0nA module.

Zero Command (Y6/7/8/9) :

When the zero output signal changes from off to on, current measured weight (offset 0, 15, 30, 45) will be a origin of gross weight (offset 5, 20, 35, 50) zero. X1 will be turned on if zeroing process was completed successfully. For successful zero, the weighing status must be stable. The status of stability can be acquired from status flags (offset 2, 17, 32, 47) of shared memory. After this command, the new origin of zero is stored in non-volatile memory and automatically restored at power on.

Tare Command (Y6/7/8/9) :

When the tare output signal changes from off to on, current gross weight (offset 5, 20, 35, 50) will be a origin of net weight (offset 10, 25, 40, 55) zero. X1 will be turned on if tare process was completed successfully. For successful tare operation, the weighing status must be stable. The status of stability can be acquired from status flags (offset 2, 17, 32, 47) of shared memory. Tare data are stored in the volatile memory and net weight is the same with gross weight at initial state such as power on.