Buffer Memory - PLCS PWM

Owned by CIMON (Unlicensed)
Mar 26, 2024
1 min read

Address

 

Item

 

R / W

Address

 

Item

Hex

Dev

Hex

Dev

0H

0

PWM output Enable

R / W

16H

22

 

1H

1

CH1,2,3,4 Frequency

R / W

17H

23

 

2H

2

CH5,6,7,8 Frequency

R / W

18H

24

 

3H

3

CH9,10,11,12 Frequency

R / W

19H

25

 

4H

4

 

 

1AH

26

 

5H

5

CH1,2,3,4 Frequency ramp control time

R / W

1BH

27

 

6H

6

CH5,6,7,8 Frequency ramp control time

R / W

1CH

28

 

7H

7

CH9,10,11,12Frequency ramp control time

R / W

1DH

29

 

8H

8

 

 

1EH

30

CH1 duty cycle ramp time(x10ms)

9H

9

Error Code

R

1FH

31

CH2 duty cycle ramp time(x10ms)

AH

10

CH1 duty cycle ratio

R / W

20H

32

CH3 duty cycle ramp time(x10ms)

BH

11

CH2 duty cycle ratio

R / W

21H

33

CH4 duty cycle ramp time(x10ms)

CH

12

CH3 duty cycle ratio

R / W

22H

34

CH5 duty cycle ramp time(x10ms)

DH

13

CH4 duty cycle ratio

R / W

23H

35

CH6 duty cycle ramp time(x10ms)

EH

14

CH5 duty cycle ratio

R / W

24H

36

CH7 duty cycle ramp time(x10ms)

FH

15

CH6 duty cycle ratio

R / W

25H

37

CH8 duty cycle ramp time(x10ms)

10H

16

CH7 duty cycle ratio

R / W

26H

38

CH9 duty cycle ramp time(x10ms)

11H

17

CH8 duty cycle ratio

R / W

27H

39

CH10 duty cycle ramp time(x10ms)

12H

18

CH9 duty cycle ratio

R / W

28H

40

CH11 duty cycle ramp time(x10ms)

13H

19

CH10 duty cycle ratio

R / W

29H

41

CH12 duty cycle ramp time(x10ms)

14H

20

CH11 duty cycle ratio

R / W

2AH

42

 

15H

21

CH12 duty cycle ratio

R / W

3FH

63

OS VERSION